Hardware design quality evaluation is expensive and centralized. Teams typically rely on expensive EDA tools (Verilator, Yosys, OpenLane) running on local infrastructure, and design competitions require coordinating independent evaluators to score submissions consistently across multiple metrics: functionality, area, delay, and power. This creates bottlenecks for validation and makes it difficult to scale open design challenges.
A decentralized network of validators, each running industry-standard EDA tools and scoring submissions against shared challenge specifications, can evaluate designs at scale with transparent, reproducible results. Validators competing for rewards through an on-chain record ladder are incentivized to evaluate accurately, while miners competing to improve their scores drive innovation.
ChipForge implements this on Bittensor subnet 108: miners download Verilog specifications and testbenches, design solutions, and submit them as ZIP files. Validators claim evaluation batches, run each design through Verilator (simulation), Yosys, and OpenLane (synthesis and timing), and submit standardized scores.
